Asseritons

SystemVerilog
,
1

Hai folks,

I have a scenario like when fifo_full signal is high then if read_en is asserted high then write_en will become low on the next clock cycle.

I have written like this →

property p1;
@(posedge clk) disableif(!reset) fifo_full |-> ##[1:3] read_en |=> write_en==0;
endproperty

read_en may assert at any time. I cannot say when it will be asserted.

could you please correct me if I am wrong.

2

In reply to Vickyvinayk:
I think this works.


property P;
@(posedge clk) disable iff (!reset)
$rose(fifo_full) ##[0:$] $rose(read_en) ##1 $fell(write_en);
endproperty
3

In reply to Bandaru sateesh:

 
first_match($rose(fifo_full)##[1:3] read_en) |=> write_en==0;

Ben systemverilog.us

4

In reply to Bandaru sateesh:

ya thanks for the response satheesh.

5

In reply to ben@SystemVerilog.us:

thank you ben. I have also seen your post regarding the first_match usage.