Array slice/part loading to the memory

SystemVerilog
,
1 

<file> load.data
// row -> 156 bit data // 'h1a0a2***aa0;
// column till 2048

reg [155:0] loc_d [0:2048];
for(int ii =0; ii < 2048; ii++) begin //{
   initial $readmemh("load.data", loc_d;
$sformatf("<PATH>.Mem[%0d] =  loc_d[%0d][51:0]",ii,ii);
// expectation: 52 bit of the loc_d should load to mem
// any help here
end //}
2

In reply to m_r_m:

You cannot execute code created from a string. What does this not do what you want:

<file> load.data
// row -> 156 bit data // 1a0a2***aa0;
// column till 2048
 
   reg [155:0] loc_d [0:2048];
   initial begin 
     $readmemh("load.data", loc_d);
     for(int ii =0; ii < 2048; ii++) 
       <PATH>.Mem[ii] =  loc_d[ii][51:0];
     end
3

In reply to dave_59:


<file> load.data
// row -> 156 bit data // 1a0a2***aa0;
// column till 2048
 
   reg [155:0] loc_d [0:2048];
   initial begin 
     $readmemh("load.data", loc_d);
     for(int ii =0; ii < 2048; ii++) 
       <PATH>.c[0].Mem[ii] =  loc_d[ii][51:0];
       <PATH>.c[1].Mem[ii] =  loc_d[ii][104:52];
       <PATH>.c[2].Mem[ii] =  loc_d[ii][155:105];
       // I can see the values in print but not able to load to the mem

//instead 
       // // row -> 156 bit data // 1a0a2***aa0;
       $readmemh("load.data", <path>.C[0].Mem,0,51);    //c[0] should gets 52 bit
       $readmemh("load.data", <path>.C[1].Mem,52,104);  //c[1] should gets next 52 bit
       $readmemh("load.data", <path>.C[2].Mem,105,155); //c[2] should gets next 52 bit
       // but still not able to load into the mem
       // any help here would helpful. 

       //$readmemh("load.data", $sformatf("<path>.C[%0d].Mem[%0d][%0d]",0, 0,51);    //c[0] should gets 52 bit
       //$readmemh("load.data", $sformatf("<path>.C[%0d].Mem[%0d][%0d]",1,52,104);  //c[1] should gets next 52 bit
       //$readmemh("load.data", $sformatf("<path>.C[%0d].Mem[%0d][%0d]",2,105,155); //c[2] should gets next 52 bit

     end