In reply to totochan1985:
Make sure your files only get compiled once
EDAPlayground compiles your code with the command line
compile testbench.sv desgin.sv
If you want any other files compiled, you need to `include them in one of those two files, or know how and where to add them to the command line.
Please read the link SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons
Then look at your corrected code