Arranging/Including classes in multiple files

SystemVerilog
5

In reply to dave_59:

In reply to totochan1985:
You never include the package.sv file or import the package. Do not include the environment.sv file

I have updated the code so you should see the package.sv file along with other changes. If I cannot `include or import the package, how do I use the package in my individual class files, environment and the testbench top to compile successfully?