I have the following code. What would be the value of S9? I think it’s 0. But not sure.
logic signed [8:0] S9_1, S9_2;
logic signed [8:0] S9;
S9_1 = -1;
S9_2 = 1;
S9 = $signed(S9_1[7:0] + S9_2[7:0]);
I have the following code. What would be the value of S9? I think it’s 0. But not sure.
logic signed [8:0] S9_1, S9_2;
logic signed [8:0] S9;
S9_1 = -1;
S9_2 = 1;
S9 = $signed(S9_1[7:0] + S9_2[7:0]);
Did you try it?
Didn’t have access to Verilog/SV simulator. Found EDA Playground. Here’s the example. Could you please explain results of “Third” and “Fourth” signed additions? Please simulate to see what I mean by “Third” and “Fourth” results.
You might be interested in looking at section 6.2 VERILOG ARITHMETIC from my book Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
I am providing that section in the following link:
https://systemverilog.us/vf/realchip357_370.pdf
This annotated example from the book may help you understand arithmetic operations in SV.
Info about Real Chip Design and Verification Using Verilog and VHDL
Addresses fundamentals in design and verification for junior engineers (types of registers, counters, memories and EDAC, metastability, transaction-based verification, control machines with FSM and microcode, arithmetic machines, synthesis.
If a design engineer does not understand these concepts he/she should look for a different career.
Forewords by Rahul Razdan (Cadence), Andrew Dauman (Synplicity).
Ebook donated for $3 Amazon.com: Real Chip Design and Verification Using Verilog and VHDL Ben Cohen VhdlCohen Publishing eBook : cohen, ben: Kindle Store
Recommended for those who lack the fundamentals of design and verification.