Append logic vector to vector

SystemVerilog
3

In reply to javatea:

Thanks to your hints.

  function automatic void slice(ref logic[255:0] in_data, ref logic[255:0] out_data, input shortint in_data_offset, input shortint out_data_pos);
    
    out_data = in_data<<in_data_offset; // shift in_data
    out_data >>= out_data_pos; // start from this position
  endfunction

It works but it will loss the original first n bits (up to out_data_pos):

before in_data  = 2222221234abcdxxxx0000000000000000000000000000000000000000000000
before out_data = eeeexxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
after  out_data = 00001234abcdxxxx000000000000000000000000000000000000000000000000
expected        = eeee1234abcdxxxx000000000000000000000000000000000000000000000000

Finally I use for-loop. It works but I want to learn a bit-shifting way. Please advise.

  function automatic void slice(ref logic[255:0] in_data, ref logic[255:0] out_data, input shortint in_data_offset, input shortint out_data_pos);
    /*
    out_data = in_data<<in_data_offset; // shift in_data
    out_data >>= out_data_pos; // start from this position
    */

    // filling out_data_pos up to last bit with in_data with offset
    for (int i = 255 - out_data_pos ; i >= 0 ; i--) begin
      int t = i + out_data_pos - in_data_offset;
      if (t >= 0 || t <= 255) begin
        out_data[i] = in_data[t];
      end
    end
    
  endfunction