APB write cycle assertion

SystemVerilog
,
9

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks. when i compiled it is failing on until_with


Error-[SE] Syntax error
  Following verilog source has syntax error :
  "testbench.sv", 18: token is 'until_with'
     $stable ((paddr) && $stable (pwdata)) until_with pready ##1 pwrite && 
  !psel && !penable);