APB READ_TRANSFER

UVM
30

In reply to PJ:

Now you have 1 clock cycle too m uch in your monitor. Look to line 244 and comment out this clock delay like this

  //     @ (this.vif.monitor_cb);
      if(tr.apb_cmd == 0)begin
         tr.data = this.vif.monitor_cb.pwdata;
       end
        else 
         tr.data = this.vif.monitor_cb.prdata;

Then you’ll see the perfect run.