Could you please suggest me on the same?
I’m new to UVM and I’m trying to verify APB protocol. I’m able to get the write section fine
But when write enable is made low, read is happening with a delay of one clock cycle. Please check and assist. Thanks in advance.
My code APB_UVM_UPDATED(copy) - EDA Playground
In reply to Athulv:
This has nothing to do with the UVM. It is the protocol what you have implemented in your driver.
Please check this with respect to the spec.
In reply to Athulv:
What do you mean by “a delay of one clock cycle”? The DUT behavior is synchronous to the clock. It senses Pen, Pwrite and Psel signals on one clock edge, then outputs the read data on the next clock edge. Do you expect something different to happen?