And operation between `defines

SystemVerilog
1

Hi,
Can we do logical and operation between two `defines? If so how?
For ex:
I have two defines A and B.
I need result like:

ifdef A && B //both should be enabled at a time $display("Both are defined"); else
$display(“Some operation must happen”);
`endif

2

In reply to Swetha Reddy E:

I suggest that you first see if there is a way of doing what you want without using ``ifdefs

But if not, you can do things like

`ifdef A
  `define A_or_B
  `ifdef B
    `define A_and_B
  `endif
`elsif B
  `define A_or_B
`endif

`ifdef A_and_B
$display("Both are defined");
`else
$display("Both are not defined");
`endif