Analysis port

UVM
1

In monitor part
Whilen connecting tlm analysis we are using new constructor method given below line
Uvm_anaylsis_port #(write_xtn) monitor_port;

Monitor_port=new(“monitor_port”,this);

My query is instead of new constructor
Why we cant use create constructor?
If we use create constructor what will happen?
Montor_port=write_xtn::type_id::create(“monitor_port”, this);

2

In reply to pradeep123:

Using the type_id::create method requires the object has to be registered with the factory. If it is not registered you have to use the new constructor.
You can try-out. Using instead of new() the type_id::create method.

3

Hi chr_sue my doubt is why we need “new” constructor for analysis port why not create, while creating analsis port in monitor?

4

In reply to pradeep123:
This was exactly what I was explaining in my last post.
Additionally whenyou are using the type_id::create method you can override this object. But this not what you want to do with an analysis port.

5

In reply to chr_sue:

What is the issue of using new?
More simple and short than type_id::create

and whats the benefits of using factory with analysis port?
If you see clear benefit than you can integrate that port to factory, but that port is just a TLM of TB architecture stuff which you create once and use through all TB lifetime.

6

In reply to haykp:

In reply to chr_sue:
What is the issue of using new?
More simple and short than type_id::create
and whats the benefits of using factory with analysis port?
If you see clear benefit than you can integrate that port to factory, but that port is just a TLM of TB architecture stuff which you create once and use through all TB lifetime.

There is no ossie using the constructor new().
The base class uvm_analysis_port is not registered with the factor. In this case you cannot use the type_id::create command, because this is the factory create command.
The consequence is you have to use the constructor new(). There is no disadvantage because the analysis ports are not intended to be overwritten.

To give you a piece of code and the corresponding error messages when using the factorx create command.
In the monitor I have the following declarations:

uvm_analysis_port #(spi_seq_item) ap;
uvm_analysis_port #(spi_seq_item) ap1;

Constructing both analysis ports using the different methods in the build_phase:

  ap = new("ap", this);
  ap1 = uvm_analysis_port #(spi_seq_item)::type_id::create("ap1", this); //line 55

Results in the following error message during compile:
** at …/tb/spi/sv/spi_monitor.sv(55): Failed to find the name ‘type_id’ in scope ‘uvm_analysis_port’ at verilog_src/uvm-1.1d/src/tlm1/uvm_analysis_port.svh(56).