An Immediate Assertion for Reset Value Check

SystemVerilog
3

In reply to ben@SystemVerilog.us:

Thanks Ben! I was hoping to catch your attention.

The change from “#0” to “final” does not work. I would like to understand in what ways is using “final” different from using “#0”.

Also, on the concurrent assertion, my idea of using the overlapping implication operator was that the increment operation is expected to work on any posedge that:

  1. ld is sampled low, and,
  2. en is sampled high, and,
  3. updn is sampled high

Request you to elaborate on why we should use a non-overlapping implication operator.

Thanks for your prompt reply.