In reply to verificator:
You can use the final.
Deferred assertions use #0 (for an Observed deferred assertion) or
final (for a final deferred assertion in the Postponed region) after the verification directive.
Corrections
upcnt : assert property (
disable iff (!rstn)
@(posedge clk)
(!ld && en && updn) // |-> q == $past(q) + 8'h1 // ERROR
|=> q == $past(q) + 8'h1
);
always @(negedge rstn)
rst_val : assert final (q == 'h0) // <------------------
$display("reset value check passed in %m");
else
$error("reset value check failed in %m");
:
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment