In reply to dave_59:
There is an implicit always associated with concurrent assertions, thus allowing the assertion to be retested at each occurrence of its clocking event. For example:
initial
ap_resetf_hi_ater_hi: assert property(@ (posedge clk)
##20 |=> always reset_f==1'b1 );
Note that assertion ap_resetf_hi_ater_hi is attempted ONCE because of the initial.
However, after 20 cycles, reset_f must always stay in the high state.
You could write this as
initial begin
repeat(20) @(posedge clk);
forever
always @(posedge clk)
ap_reset_f_hi: assert property(reset_f==1'b1 );
end
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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