Always_latch counter example doubt

SystemVerilog
1

I’m going through system verilog and doing some examples . I was doing one example of counter.
Specification is: 5 bit counter, logic generates latched enable signal based on start signal,
Counter starts counting, once reaches max counter .overflow is asserted and enable goes low.
Below is the snippet of code. I have run simulation and my doubt is how overflow signal gets asserted after reaching max count.
Please help me to understand as I was new to SystemVerilog.

logic [4:0] counter;
always_latch begin
     if(!resetN)
  	   enable <= 0;
     else if(start)
  	   enable <= 1;
     else if(overflow)
  	   enable <= 0;
 end

 always @(posedge clk, negedge resetN) begin
     if(!resetN)
  	   {overflow, counter} <= 0;
     else if(enable)
  	   {overflow, counter} <= read_pointer +1;
 end
2

I assume max counter means 5’b11111. It would also help to show the declarations of all the variables used in your snippet.

When you have a concatenation on the the left-hand-side of an assignment, it behaves as a variable the width of the concatenation. So assuming overflow is a 1-bit variable, your concatenation is a 6-bit variable. The expression on the right-hand-side is at least 32-bit wide. That is because a number literal is implicitly 32-bits, and the the result of an addition is as wide as its widest operand. See section 11.6 of the SystemVerilog 1800-2012 LRM.