Always block equivalent construct

SystemVerilog
1

I am trying to model a Design in SV for verification purpose.

I am looking for construct which works similar to always block in verilg but can eb used inside class

eg: always(posedge clk, reset)

I am looking for some construct which works the same but can be used inside a class.

I am assuming, we can not use always block in a class

2

Hi Bhaskar,

Always block cant be used inside a class.
I can suggest you to use forever block inside the class which meets your requirments of always block inside a class
For More information visit

3

Assuming you are in a task like run (OVM) or run_phase(UVM), you can always do

task run;
fork
   forever @(posedge v_itf.clk) 
              begin
              ...
              end
join_none
endtask

Dave Rich
go.mentor.com/drich

4

In reply to dave_59:

Hello Dave

I am actually looking for an equivalent for
always @(posedge clk, negedge resetn) begin
code1;
end

where I can have the sensitivity list for the same block of code.

The same can be written using fork join as shown below:
fork
forever @(posedge clk)
begin
code1;
end
forever @(negedge resetn)
begin
code1;
end

join_none
Here I am duplicating code1. which I want to avoid.
Can you give me an example where I can have sensitiity list used in classes.

5

In reply to pbhaskar:

Syntactically, you can put anything after forever that you can put after always. So you can have

fork
  forever @(posedge clk, negedge reset)
      begin
         code1;
      end
join_none