Ahb bus arbiter

SystemVerilog
1

How can i control the duty cycles between request and grant in an ahb bus arbiter using system verilog assertions,in order not
to transcend a limit such as ##10 between req and grant and then if this limit is outreached an error message should be displayed.
And secondly,how can i control by creating a system verilog assertion if two grant signals are simultaneously active?

2 
/*How can i control the duty cycles between request and grant in an ahb bus arbiter using system verilog assertions,
  in order not to transcend a limit such as ##10 between req and grant and then 
  if this limit is outreached an error message should be displayed. */

// Two choices: 1) You could define that duty cycles limit as a parameter 
//              2) Define it as a variable and use that in a property with local variable 
//                 for example
module m;
	parameter int d=10; 
	int dc=10; 
	bit clk, req, ack; 
	
	p_with_parameter: assert property(@(posedge clk) req |-> ##[1:d] ack);
		
     property p_with_var; 
     	int v_dc; 
     	(req, v_dc=dc) |-> ##[1:$] (ack, v_dc=v_dc-1'b1)[*1:$] ##0 v_dc==0; 
	 endproperty :  p_with_var
	a_p_with_var: assert property ( @(posedge clk) p_with_var); 
endmodule : m
/*And secondly,how can i control by creating a system verilog assertion if two grant signals are simultaneously active?*/
/*  See 
   https://verificationacademy.com/forums/systemverilog/sva-question-0
*/

Ben Cohen Training for VMM, SVA (831) 345-1759
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
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  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115