Advantages of System Verilog Over C Language

SystemVerilog
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1

Let’s say I would like to generate a sinusoidal real valued signal.

There are two ways to generate it:
[1]: I can generate it using purely system verilog codes
[2]: I can generate it using C language

Now, if C language has been used, then, DPI-C is required to interact with System Verilog and ultimately, which will produce a sinusoidal wave in real valued.

The desired signal should be real valued signal.

Now, which one between [1] and [2] said above, will be the optimum way to generate a sinusoidal signal?

Any lucid elucidation will be highly appreciated.

Thank you.

2

In reply to babunp114525:

In either language they are going to be discrete approximations of a continuous time domain. You need to consider how much computational effort it takes to generate this signal versus the rest of the system. SystemVerilog provides direct access to real math function without requiring the use of DPI-C.

If the math is needed in C anyways for some other application, you don’t want to have to write it twice and maintain two different version.