In reply to ben@SystemVerilog.us:
NOTE: Formal input args passed by value receive sampled actual arguments.
Thus, for …@( posedge clk ) a |-> c ##cnt ##0 b ; // illegal if cnt is dynamic
and I wanted to use a task that computes this consequent then I could pass the argument c to the task.
// removed the debugging stuff for simplicity
task automatic dynamic_delay2( int cnt, bit c );
// @( posedge clk ) a |-> c ##cnt ##0 b ;
am_cb: assert(c); // the actual is the sampled value
if($sampled(c) && cnt > 0 ) begin
repeat( cnt ) @( posedge clk );
// NO NEED to Changed b to $sampled( b )
am_b: assert(b); // b's value == $sampled(b)
end
endtask
property prop;
@( posedge clk ) a |-> ( 1, dynamic_delay2( val, c) );
endproperty
assert property ( prop ); // PASSes if a==1, it never failsc
Ben