Achieving Dynamic delays in SVA using subroutine

SystemVerilog
,
5

In reply to ben@SystemVerilog.us:

Thanks Ben for pointing the following :

Also, b may have schaged value if it was updated in the NBA region.
You should use $sampled(cnt) instead of cnt.

Hence in your solution to the original question at the top :


task automatic dynamic_delay2( int cnt );  
    $display("Task called at T:%0t with i/p arg == %0d",$time,cnt);
    if( cnt > 0 ) begin      
       repeat( cnt ) @( posedge clk );

// Changed to $sampled( b ) so that pre-poned value is used incase b is updated in NBA region
       am_b: assert( $sampled(b) ) $display("Assertion Pass"); 
         else  $display("Assertion Fails");
       $display("Task completes at T:%0t",$time);
     end   
  endtask
 
    property prop;       
      @( posedge clk )  a  |->  ( 1, dynamic_delay2( val ) ); //  ##0 b ;
    endproperty
 
    assert property ( prop ); // PASS/FAIL within task