Hi
I have an issue accessing(for read) memory array inside some memory model which is a part of verilog testbench top_tb
In the scoreboard i have to compare expected bytes constructed in monitor class to actual bytes located inside this verilog memory array
Previously i have built uvc component using Specman eRM where accessing some Verilog array from specman unit is easy but how it is done in UVM
I know that I cannot declare fields of SV interface to be an array, am I right?
What can be done to solve this?
Hello,
Yes you cannot declare array in interface.
In this case using Backdoor access to memory is best choice.
Here, you Create Abstract class and pure virtual method(Read/write) and implement this method in TOP file from where DUT hierarchy of Memory is visible.
If you correctly set object of Implemented class from top then you can get this obj anywhere in TB component(in your case scoreboard) and access that memory array using this function.
You will find example code here.
In reply to Vinay Jain:
BTW, I like to use the 1800-2012 interface class when an abstract class only contains pure virtual methods. That way I can define it as
interface class abstract_bd_access;
without extending it from uvm_object. Then I can define
class backdoor_access extends uvm_object implements abstract_class_pkg::abstract_bd_access;
This way abstract_bd_access is not dependent on uvm_object and I define concrete classes extended from other classes like uvm_component if I want to.