Accessing the UVM RAL model handle inside the testbench module

UVM
,
5

In reply to chr_sue:

I am creating the RAL model inside the env class build method and I am calling the uvm_config_db::set() method inside the connect() phase as follows.

if(PCRMLP_REG == null) begin
PCRMLP_REG=_pcrm_lp_reg_mmap_type::type_id::create(“PCRMLP_REG”,this);
PCRMLP_REG.build();
PCRMLP_REG._pcrm_lp_reg_rf.set_hdl_path_root(“DUT PATH”);
PCRMLP_REG.lock_model();
PCRMLP_REG.default_map.set_auto_predict(.on(0));
end

if(PCRMHP_REG == null) begin
PCRMHP_REG=_pcrm_hp_reg_mmap_type::type_id::create(“PCRMHP_REG”,this);
PCRMHP_REG.build();
PCRMHP_REG.lock_model();
PCRMHP_REG.helios_pcrm_hp_reg_rf.set_hdl_path_root(“DUT PATH”);
PCRMHP_REG.default_map.set_auto_predict(0);
end

uvm_config_db#(helios_pcrm_lp_reg_mmap_type)::set(this, “", “PCRMLP_REG”, PCRMLP_REG);
uvm_config_db#(helios_pcrm_hp_reg_mmap_type)::set(this, "”, “PCRMHP_REG”,PCRMHP_REG);

uvm_config_db::get() method is called inside the initial block to get the RAL handle after some random non-zero delay to allow the UVM hierarchy to be built-up as I have mentioned in the first post in this thread.