Accessing enum type of data

SystemVerilog
4

In reply to dave_59:

Hi Dave,

Pardon me for having vague questions. No, I am not asking about declaring an associative array indexed by an enum. I want to understand whether SV LRM do mentioned that the following code of accessing and assigning enum variables are allowed or not. Do take note that the code is not using typedef. It is declaring enum fruits and directly assigning it as shown in the line (1) and line (2).

module top();
  enum bit[31:0] {apple, banana, tomato} fruits;
  initial begin
    fruits[apple] = 1'b1; // --- 1
    furits[tomato] = 1'b0; // --- 2
  end
endmodule.