Accessing enum type of data

SystemVerilog
3

I don’t understand what is being asked. You can certainly declare an associative array indexed by an eunum type.

module top;
 typedef enum {apple, banana, tomato} fruit_e;
 bit fruits[fruit_e]; // associate array of a bit.
  initial begin
    fruits[apple] = 1'b1; // --- 1
    furits[tomato] = 1'b0; // --- 2
  end
endmodule