Accessing complex arrays in system verilog

SystemVerilog
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1

how to access the below arrays bit-wise, slice-wise and block-wise ?

logic [3:0][7:0]data[15:0]

logic [3:0][7:0]mem
2

In reply to svishnu:


data[15][3][7] //bit
data[15][3] //byte
data[15] //word