In reply to Sailaja:
You must remember that macros are pre-processor compiler directives that substitute text for their arguments before any SystemVerilog syntax is parsed
When you invoke the macro `my_object_reg(a_var), you are not passing a variable, but a token of text. That token of text will be substituted to form what will become a variable name and a string.
VtssUvmObject uvm_obj_hdl_a_var = VtssUvmObject::get_handle("a_var");
The line
int interm = this.`field_name("a_var");
should have expanded to
int interm = this.""a_var"";
and produced a compiler error. If you are using Questa, you can use vlog -E file to have the output of the pre-processor saved in a file. If it does not produce a compiler error, then that is likely a tool bug.