Accessing class variables in a for loop

SystemVerilog
,
3

In reply to cgales:

Hi,

On the similar lines, I have a question:
We can form a string from a variable name using defines and ".
Similarly can we form a variable name from a string and use it?

Example:

  `define my_object_reg(NAME) \
     VtssUvmObject uvm_obj_hdl_``NAME = VtssUvmObject::get_handle(`"NAME`");

This macro if I call like this:

class cl;
int a_var;
`my_object_reg(a_var);
endclass:cl;

It would create a handle uvm_obj_hdl_a_var of type VtssUvmObject, and also passes the string argument (“a_var”) to the get_handle function call.

Similarly, if I have a string “a_var”, can I use some sort of define macros to convert string to a variable name? I tried below but I dont think it completely works:

`define field_name2(ARG) ARG
     `define field_name(ARG) `field_name2(`"ARG`")

So if I call somewhere in the above class:

class cl;
int a_var;
`my_object_reg(a_var);

function void display_val();
int interm = this.`field_name("a_var");

$display("Value present in this.a_var is %0d",interm);
endfunction:display_val;

endclass:cl;

I just tried to use one field_name macro to get the variable name from string, but I could not get it compiling, so I used two nested macros, which got compiled, but the display prints some value other than what a_var was assigned to.