Accessing a memory inside a memory model, through backdoor

UVM
1

Hi,
I am a new UVM user. I am trying to access a memory instantiated inside a memory model ( say DDR2 model) using the UVM backdoor accesses. I have used backdoor accesses for registers inside the DUT, but have not been able to extend the same , to this particular scenario.

So, this is what I have:

DUT : begin

//Instantiates a DDR model

 DDR_model : begin

    //has a sparse memory called "mem" say..
    //DUT writes/reads this mem thro the actual DDR protocol.
    //Goal is to get the UVM side to be able to access this mem too.

end : DDR_model

end : DUT

What I want to do :
From any seq ( say top_seq_lib ), be able to do this:
1.Init “mem”.
2.Rd/Wr locations in “mem”.

BIG picture questions:
1.How will the UVM side be able to see “mem”?
2.For the reg model inside the DUT, we ahve this in the env.build:

uvm_reg::include_coverage("*", UVM_CVR_ALL);
    if (reg_model == null) begin
        reg_model = ddr_reg_model_c::type_id::create("reg_model");
        reg_model.build(); 
        reg_model.lock_model();
         reg_model.set_hdl_path_root("DUT.ddr_ctrl.csr_u");
    end

Can we use the “set_hdl_path” somehow, for the memory inside the DDR model.

  1. Since I do not have a frontdoor mechanism ( like AHB) to access this memory, I think as a workaround I can make this memory part of a class and use the class methods to rd/wr this mem. If this is correct , will I be able to use these methods hierarchically from the uvm side.

4.Would it be best to define a verilog wrapper in the model - around the memory - that accesses the meory based on some register settings - the registers being set from the UVM side, using backdoor access?

WHat is the best way to do this?

Any help would be highly appreciated.

Thanks & regards