Accessing a generate block hierarchy

SystemVerilog
6

In reply to dave_59:

Hi Dave,
I’m trying to something similar but for binding my assertions.
Below is my bind statement in my bind assert module:

define NUM_BLKS 4; genvar asrt_inst; generate for (asrt_inst = 0;asrt_inst < NUM_BLKS;asrt_inst = asrt_inst+1)
begin
bind top.u_dut.u_blk_gen[asrt_inst] my_assert u_my_assert (
.
);
end
endgenerate*

Here, the RTL is under gen block of u_blk_gen[gen_var], and I’m trying to bind my assertion to each instance of the generated instance.
The path instances of the RTL, generated using the generate block are :

  1. top.u_dut.u_blk_gen[0]
  2. top.u_dut.u_blk_gen[1]
  3. top.u_dut.u_blk_gen[2]
  4. top.u_dut.u_blk_gen[3]

And with the bind statement, I get the below compile error:
*
bind top.u_dut.u_blk_gen[gpt_asrt_inst] my_assert u_my_assert (
|
ncvlog: E,ILLGVR (/home/user/assertion_bind.v,165|72): This genvar cannot be used in this context [12.1.3(IEEE 2001)].

Is there a work around for such scenario?