In reply to dave_59:
Hi Dave ,
When we set the instantiated interfaces into uvm_config_db# from within the initial block which is inside the generate-for loop, there could be potential race condition between when the run_test() call and these interfaces are set in config_db# because they will be in different initial blocks . I have my bench structure where these interfaces are instantiated in a nested module within the top level module . I’m calling run_test() from initial block of top level module.
module tb_top
master m();
initial begin
m.set_rtl_interfaces();
run_test();
end
endmodule
module master();
virtual vbus_mgt_interface vbus_mgt_if_array[PORT_NUM]; // temp virtual interface array generate for(genvar i=0;i<PORT_NUM;i=i+1) begin: vbus_connect
vbus_mgt_interface vbus_mgt_if(
.ppc(drd_usb_vbus_ppc),
.ovc(),
.vbus_p(vbus_p_bfm),
.id(drd_usb_id)
);
initial begin
vbus_mgt_if_array[i] = vbus_mgt_if;
end
end
endgenerate
function void set_rtl_interfaces();
for(int i=0;i<PORT_NUM;i=i+1) begin uvm_resource_db #(virtual vbus_mgt_interface.TB_PWR_CONNECT)::set_anonymous($psprintf({TOP_USB_ENV,“.drd_env[%0d].vbus_agent[%0d].driver”},i,i),vbus_mgt_if_array[i].TB_PWR_CONNECT);
end
endfunction : set_rtl_interfaces
endmodule
If we want to avoid the initial block in module master , we need direct access of the different instances of interface instantiated within the generate for loop.
Thanks,
Chandra