In reply to seyaleli1234:
What makes you think you cannot use a generate block in SystemVerilog? If it was in Verilog–it is in SystemVerilog. You can put your uvm_config_db::set in the initial block that is inside the generate-for loop.
In reply to seyaleli1234:
What makes you think you cannot use a generate block in SystemVerilog? If it was in Verilog–it is in SystemVerilog. You can put your uvm_config_db::set in the initial block that is inside the generate-for loop.