Accessing a generate block hierarchy

SystemVerilog
10

In reply to dave_59:

Hi Dave,
Below is the RTL module dut code snapshot where u_blk is instantiated using generate block:


`define NUM_BLKS 4

localparam [5:0]PARAM1_ARY[3:0]  = '{16,16,32,40};
localparam [1:0]PARAM2_ARY[3:0]  = '{1,2,2,3};


genvar blk_inst;
generate
for (blk_inst = 0;blk_inst < `NUM_BLKS;blk_inst = blk_inst+1) 
  
begin : u_blk_gen
       blk   #(
                .PARAM1(PARAM1_ARY[blk_inst]),
                .PARAM2(PARAM2_ARY[blk_inst])
              )
        u_blk (
                .* //ports mapping done here
              );
end
endgenerate

For the above RTL code, the instance’s path I see it in the waveforms is as below:


top.u_dut.u_blk_gen[0].u_blk
top.u_dut.u_blk_gen[1].u_blk
top.u_dut.u_blk_gen[2].u_blk
top.u_dut.u_blk_gen[3].u_blk

For the above RTL, I’m trying to bind my assertion as below in a similar fashion wherein even by assertion module has the same parameters:


localparam [5:0]ASRT_PARAM1_ARY[3:0]  = '{16,16,32,40};
localparam [1:0]ASRT_PARAM2_ARY[3:0]  = '{1,2,2,3};

genvar asrt_inst;
generate
for (asrt_inst = 0;asrt_inst < `NUM_BLKS;asrt_inst = asrt_inst+1) 
begin 
bind top.u_dut.u_blk_gen[asrt_inst].u_blk my_assert #(
                .PARAM1(ASRT_PARAM1_ARY[asrt_inst]),
                .PARAM2(ASRT_PARAM2_ARY[asrt_inst])
              )
u_my_assert 
(
.*//ports mapping done here
);
end

endgenerate

And below is the compilation error I get:


file: /home/user/assertion_bind.v
bind top.u_dut.u_blk_gen[asrt_inst].u_blk my_assert #(
                                  |
ncvlog: *E,ILLGVR (/home/user/assertion_bind.v,167|68): This genvar cannot be used in this context [12.1.3(IEEE 2001)].
	module worklib.assertion_bind:v