Access a module in generate block hierarchy

SystemVerilog
4

In reply to SandipGajera:

  1. You need data types for your arguments; otherwise it assumes they are 1-bit. Also, you should use a function instead of a task for any routine that does not consume time. (no blocking statements)
  2. You have written a procedural assignment outside of a procedural context, and then you are trying use new() on the entire array - you can only use new() on one element at a time. You can call new() in the declaration initialization of device_data_element_h, or you can move the assignment into the initial block. But there’s an easier way that doesn’t involve the intermediate device_data_element_h variable. I’ll show that in an example.
  3. You will need to put the device_data_array class and handles in a package so that it can be shared with this module and any other module or package.
package dev_data_pkg;
 
virtual class device_data_array_c; // this could also be an interface class
  pure virtual function void out_data_transfer(int ep_num,data_lenth);
  pure virtual function void in_data_transfer(int ep_num,data_lenth);
endclass
 
device_data_array_c device_data_array_h[int];

endpackage

module abc;
import dev_data_pkg::*;

localparam MAXPRT = 8;

genvar index;
  for(index = 0; index < MAXPRT; index++) begin :class_decl_loop
  class device_data_element_c extends device_data_array_c;
    function void out_data_transfer(int ep_num,data_lenth);
      dev_env[index].dut2_env.out_data_transfer(ep_num,data_lenth);
    endtask
 
    function void in_data_transfer(int ep_num,data_lenth);
      dev_env[index].dut2_env.in_data_transfer(ep_num,data_lenth);
    endfunction
  endclass
 
  initial 
    device_data_array_h[index] = device_data_element_c::new() 
end : class_decl_loop
 
endmodule :abc