Access a module in generate block hierarchy

SystemVerilog
3

In reply to dave_59:

Hi Dave,

Thanks for quick help.my problem is still not solved yet.

Three problems are there:

  1. I want to pass input arguments in my tasks ‘out_data_transfer’ and ‘in_data_transfer’.
    So please let me know that following code will work for this requirements ?
  2. In following code, line “device_data_array_h = new();” gives error in Questa Sim and the error is :
    near “=”: syntax error, unexpected ‘=’, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.
    If I add this line in initial block then it gives error : ‘new’ expression can only be assigned to a class or covergroup variable.
    but in this case ‘device_data_array_h’ is already a class
  3. Also I want to access variable from ‘dut_env’ module,Is it possible without task or function ?

//========================================================================
module abc;

localparam MAXPRT = 8;

virtual class device_data_array_c;
  pure virtual task out_data_transfer(ep_num,data_lenth);
  pure virtual task in_data_transfer(ep_num,data_lenth);
endclass

device_data_array_c device_data_array_h[MAXPRT];

genvar index;
  for(index = 0; index < MAXPRT; index++) begin :class_decl_loop
  class device_data_element_c extends device_data_array_c;
    task out_data_transfer(ep_num,data_lenth);
      dev_env[index].dut2_env.out_data_transfer(ep_num,data_lenth);
    endtask
    
    task in_data_transfer(ep_num,data_lenth);
      dev_env[index].dut2_env.in_data_transfer(ep_num,data_lenth);
    endtask
  endclass

  device_data_element_c device_data_element_h;
  device_data_array_h = new(); 

  initial 
  begin
    // device_data_array_h = new(); 
    device_data_array_h[index] = device_data_element_h;
  end
    
end : class_decl_loop

endmodule :abc
//========================================================================