About cycle accurate predictors

SystemVerilog
, ,
1

My question is multifold and sort of vague because I do not completely understand this, so here it goes -

  1. What is a good accepted methodology for cycle accurate predictors (which is in lockstep with the design)? Specifically, what are the different ways one could model pipeline delays (track cycles in run_phase of that predictor component, etc…)?

  2. If one were to implement the same kind of predictor in C/C++ and use DPI calls, how would one model pipeline delays in said C/C++?

I realize the second question is not system verilog, but nonetheless, in the general interest of verification.

2

In reply to kernalmode1:

Ping.
Still trying my luck to see if anyone responds