Hi ,
I have a few basic questions related to SystemVerilog Assertions :
(1) Both ‘&&’ and ‘and’ are boolean operators, so when should prefer one over the other ?
One reason I could think of is that, using 'and' operator we could have a sequence_expression on both sides :
assert property( @(posedge clk) ( a ##3 b ) and ( c ##2 d ) ); // Using '&&' instead of 'and' gives compilation error
Are there any more reason(s) ?
(2) Both ‘||’ and ‘or’ are boolean operators, so when should prefer one over the other ?
Similarly using ‘or’ operator we could have a sequence_expression on both sides :
assert property( @(posedge clk) ( a ##3 b ) or ( c ##2 d ) ); // Using '||' instead of 'or' gives compilation error
Are there any more reason(s) ?
(3) cover property is used for coverage . From a syntax perspective are there any restrictions on what is legal within cover property compared to assert property ?
If a code is legal within assert property, will it also be considered legal within cover property ?
(1) Both ‘&&’ and ‘and’ are boolean operators, so when should prefer one over the other ?
Both ‘||’ and ‘or’ are boolean operators, so when should prefer one over the other ?
It’s easy for me to give you the answers, but I would rather that you do some work and figure out the answer.
QUestion for you: Where in 1800 do you see that the “and/or” are boolean operators?
Do a search and tell me what kind of operator they are and what they mean.
(3) cover property is used for coverage . From a syntax perspective are there any restrictions on what is legal within cover property compared to assert property ?
If a code is legal within assert property, will it also be considered legal within cover property ?
Again, a question for you: Do you see any difference in the syntax?
What happens when the property succeeds? what if it fails?
Do a search in 1800 and give me the answers.
BRW, I am saying all of this because I want you to learn.
Over the years, I provided many answers and learned that feeding the answers does not teach very much.
Ben Cohen Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.