A constraint to generate odd_even_odd....... etc sequence

SystemVerilog
, ,
4

You can also use const’ in the constraint, which gives the previously randomized value.


class packet;
    rand bit [7:0] x;

    constraint c {(x % 2) != (const'(x) % 2);};
endclass : packet

module tb;
    packet packet_h;

    initial begin
        packet_h = new;

        repeat (10) begin
            if (!packet_h.randomize) $finish;
            $display ("x = %b", packet_h.x);
        end
        $finish;
    end
endmodule : tb