In reply to Omran:
import uvm_pkg::*; `include "uvm_macros.svh"
module blk;
class test;
rand bit [7:0] x;
bit w;
constraint c1 {x%2==w;}
endclass : test
initial begin
test t1=new();
repeat(10) begin;
// void'(t1.randomize());
// BETTER methodology
if (! t1.randomize()) `uvm_error("MYERR", "This is a randomize error")
t1.w= !t1.w;
$display("t1.x=%h", t1.x);
end
end
endmodule
t1.x=b4
t1.x=91
t1.x=24
t1.x=1d
t1.x=64
t1.x=b5
t1.x=14
t1.x=27
t1.x=4c
t1.x=ef
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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