A constant SVA cycle delay within a range?

SystemVerilog
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6

In reply to warnerrs:

I did find a good generate loop for that code. After I converted $past(a,#) to a shift register, the solution became apparent.


	assign     n_observed_delay[0] = observed_delay[0] ||   past_a[0] && /*!past_a[-1]*/  && b;
	for( genvar N=1; N<=10; N++ ) begin: delay
	    assign n_observed_delay[N] = observed_delay[N] || ( past_a[N] &&   !past_a[N-1:0] && b );
	end