A constant SVA cycle delay within a range?

SystemVerilog
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2

In reply to warnerrs:
You could do something like to measure the needed delay.


/* If the variable used to define the delay has values that are within a constraint range, such as between 0 and 7 (or 15, or at most 32) one can use the generate statement, which appears much simpler than the use of local variables and the sequence_match_item. Example: */
let v=10;
let max= 10;
let s=0;
generate for (genvar g_i=s; g_i<max; g_i++) begin
  ap_delay_gen: assert property (v==g_i && $rose(a) |-> ##g_i b);
end endgenerate

Then when you find out which value works for you, set the values of the lets. For example, assume that the assertion that works OK is with a dely of 5. You can then change the lets to:


let v=5; // your desired delay
let max= 6;
let s=5;
// The generate statement is NOT changed. 
generate for (genvar g_i=s; g_i<max; g_i++) begin
  ap_delay_gen: assert property (v==g_i && $rose(a) |-> ##g_i b);
end endgenerate

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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