2-D dynamic array of parameters failed

SystemVerilog
, ,
2

In reply to amy992:

Parameters are evaluated at elaboration time.The elaboration time flattens out the module/program hierarchy, propagates the appropriate parameter overrides and resolves hierarchical references to different modules.

So, a parameter must not be dynamically allocated array. It should be elaboration time constant variable or array. There should not be any overriding of parameter after elaboration time. Note that the elaboration time is not the simulation time-0.

In order to pass varying sizes of parameters, you can add the dimensions of parameter array as another parameters. For example, you can add the ROWS and COLS parameters which defined the number of elements in the STATE_ARRAY:

module mymod #(
parameter int ROWS = 2,
parameter int COLS = 2,
parameter int STATE_ARRAY [ROWS] [COLS] = '{'{30, 100}, {24,155}}) (/*some ports*/);
//...

module top();
  // Override the ROWS parameter
  mymod #(.ROWS(3), .COLS(2), .STATE_ARRAY('{'{30, 100}, {24,155}, {1,2}})) m();
endmodule

// Output:
ROWS= 3 COLS=2
STATE_ARRAY[0][0] = 30
STATE_ARRAY[0][1] = 100
STATE_ARRAY[1][0] = 24
STATE_ARRAY[1][1] = 155
STATE_ARRAY[2][0] = 1
STATE_ARRAY[2][1] = 2

module tio();
  mymod m();
endmodule

// Output:
ROWS= 2 COLS=2
STATE_ARRAY[0][0] = 30
STATE_ARRAY[0][1] = 100
STATE_ARRAY[1][0] = 24
STATE_ARRAY[1][1] = 155

This post can be useful about passing array of parameters to a module.