2-complement add/subtract

SystemVerilog
1

Hi,
please consider the next case:

bit[44:0] address;
rand bit signed [43:0] add_or_sub_from_adress;
bit [63:0] result;

I’m trying to perform result = address + add_or_sub_from_adress;
but since the bits length of address and add_or_sub_from_adress are different I get wrong result when add_or_sub_from_adress is negative.

Any idea how should I do it correctly?

Thanks,
Moshiko

2

In reply to moshiko:

When mixing signed and unsigned operands in SystemVerilog, the result becomes unsigned. Sign extension only occurs to signed parts of the expression. So in this case, there is no sign extension. You need to cast the signed operand out to the width of the result.

result = address + 64'(add_or_sub_from_adress);