1Ghz multiple clocks generation using loop

SystemVerilog
, , ,
1 

module test;
timeunit 1ns;
timeprecision 100ps;
bit [15:0] clk; 
realtime delay=0.5ns; // 1GHz
 
always begin
     for(int i =0; i <16; i++) begin
     fork
        #delay clk[i] =~ clk[i]; // 1 Ghz clock for 16
     // i am getting phase shifting for all the clock
     join
     end
  end
 
initial
  begin 
   #2ms;
   $finish;
  end
endmodule

any alternate best way to generate multiple clocks for the above scenario w/O phase shifting? thanks

2

In reply to m_r_m:

It’s not clear why you are using a for loop. What do you want the 16 clocks to look like if not identical values? Also, using a fork/join block with one statement makes no sense. It is the same as using a begin/end.

3

In reply to dave_59:

I am trying to generate 16 same frequency clocks and pass to the 16 inputs, please refer the link for snap.

  1. could you please suggest an alternate to the for loop?
  2. I would need 16 clocks for the 16 instance of the DUT.
  3. without the fork/join, i’m not getting 16 clocks, getting only clk[0].
4

In reply to m_r_m:

always begin
        #delay clk =~ clk; // 1 Ghz clock for 16
  end

This assumes al 16 bits of clk toggle the same. It’s not even clear why clk needs to be 16 bits of al bits are alway the same value. You can connect the same bit of a single bit-clock to each DUT.