Write address bit toggle coverage in terms of functional coverage

SystemVerilog
1

Hi,

if I have a parameterized address signal and i would like to write functional coverage for toggling each bit 0 → 1 , whats the best way to write it ? which mean write toggle coverage in terms of functional coverage.

module test;
parameter ADDRESS_WIDTH = 32;

logic [ADDRESS_WIDTH-1 :0] addr;

endmodule

2

In reply to sv_uvm_learner_1:
See https://verificationacademy.com/forums/systemverilog/bitwise-toggle-coverage-bitvector#reply-38133

3

Hi Dave

Do you have any logic for writing both 0=> 1 and 1 => 0 toggling of bits