Dear Forum,
Can someone please provide some explanation why someone needs to use System Verilog Soft constraint.
Thanks
In reply to haykp:
Soft constraints can be useful in cases where you may need to extend a set of constraints that include error conditions or illegal conditions. There are other situations where soft constraints can come in handy but I’ve used this one a lot in the past.
For example, perhaps your transaction involves an array of data whose size must be a multiple of two, but the design under test needs to be able to handle cases where the incoming data is of an illegal size.
In this situation, the base class for the transaction would contain a “soft” constraint to keep the size of the data array on an even boundary, but an extended class could produce illegal data sizes by declaring an additional “hard” constraint that make the size end on an odd boundary. Since the original constraint was declared as “soft” it will not be in conflict with the new constraint in the extended class, allowing you to produce illegal stimulus when the need arises.
In reply to haykp:
I asked this question a while back and here are some additional points to what jcraft mentioned
HTH,
-R
Thank you soo much!
But all these functionality we can reach by using hard constraints, by using constrain_mode on/off.
So we can turn off the hard constraint and redefine new constrain. Isnt this mode safe?
In reply to haykp:
To use constraint mode on/off you need to know the constraint name with soft constraints you don’t, imagine the case you get a VIP that is encrypted you cannot access the source code maybe in this case it could useful.
HTH,
-R