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  • SV soft constraints usage and benefits

SV soft constraints usage and benefits

SystemVerilog 6436
rgarcia07
rgarcia07
Full Access
221 posts
March 16, 2018 at 1:41 pm

Hello verification experts,

This is something that has been puzzling me for a while I know there is this keyword in constraints 'soft', but I'm not sure about its usage, I've heard about soft constraints in specman but never used them, what is the benefit, if you need to 'override them' you can extend from the class containing the orignal constraint and write a new one with the same name (please correct me if I'm mistaken) or you could use some array of knobs to change its behaviour as described by Dave in this thread which doesn't seem to difficult to implement.

From the 1800-2012 LRM I see section 18.5.14 I read the idea of more complete and easily to extend verification environments and IPs, but in the end IMHO it may lead to unintended 'negative testing' since maybe the engineer using this environment is wrongly creating invalid scenarios with new constraints.

Can somebody please provide an example and reasoning behind this construct, and its usage (not the ones in LRM) and apologies for the lengthy post.

Cheers,

-R

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cuonghle
cuonghle
Full Access
305 posts
March 16, 2018 at 9:34 pm

In reply to rgarcia07:

I'm not really sure, just wait other people to confirm. However, sometimes I think, we override a constraint is more difficult: Let's say my constraint have 100 instruction lines and I just want to change one of them. If you use overridden method, you have to rewrite all 100 lines in that constraint, right? Using 'soft' is easier in this case.

Chris Le

Solution

Solution

dave_59
dave_59
Forum Moderator
10869 posts
March 17, 2018 at 8:33 pm

In reply to rgarcia07:

a. The user doesn’t need to explicitly know the name of the constraint block in order to disable the soft constraint, just the name of the variable.

b. It would be possible for the class writer to put several soft constraints within the same named constraint block and still allow the user to disable the soft constraints one at a time.

c. The soft constraint can be overridden from within the randomize () with {} block, rather than outside the block

d. The soft constraint can be temporarily overridden in a 1-shot manner, without having to disable before randomize() and enable after randomize()

See the original proposal

— Dave Rich, Verification Architect, Siemens EDA

rgarcia07
rgarcia07
Full Access
221 posts
March 17, 2018 at 9:14 pm

In reply to dave_59:

Thank you Dave for the explanation it makes a lot of sense.

bl4ckp3rl
bl4ckp3rl
Forum Access
42 posts
September 03, 2021 at 12:18 am

In reply to dave_59:

Hello Dave,

"a. The user doesn’t need to explicitly know the name of the constraint block in order to disable the soft constraint, just the name of the variable"

Tried an example for above statement 

class packet;
  rand  bit [3:0] addr;
 
  constraint addr_range { soft addr inside {5,10,15}; }
endclass
 
 module static_constr;
  initial begin
    packet pkt;
    pkt = new();
 
 
    $display("Before Constraint disable");
    repeat(2) begin //{
      pkt.randomize();
      $display("\taddr = %0d",pkt.addr);
    end //}
 
    //disabling constraint
    pkt.addr.constraint_mode(0);
 
    $display("After Constraint disable");
    repeat(2) begin //{
      pkt.randomize();
      $display("\taddr = %0d",pkt.addr);
    end //}
  end
endmodule

Error:-Could not find field/method name (constraint_mode) in 'addr' of 'pkt.addr.constraint_mode

->Could you please let me know ,if i miss interpreted the statement ?
Thanks in Advance

dave_59
dave_59
Forum Moderator
10869 posts
September 03, 2021 at 8:49 am

In reply to bl4ckp3rl :

You still would need to write pkt.addr_range.constraint_mode(0); to explicitly disable the constraint. The point of that statement is that you could write

pkt.randomize() with {addr == 11;};

without using the constraint_mode setting.

— Dave Rich, Verification Architect, Siemens EDA

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