I am new to SystemVerilog. So the following is certainly a basic question, but it has caused me a lot of trouble.
Where is the best place to put an include statement? I have written a number of testbenches now that define classes and types that are referenced in other files. Sometimes I need to pass a type defined in a header file through a module port mapping. Since I have done a fair amount of C/C++ programming, I assumed that the include is like a include, and that I should simply position it before the module port mapping:
`include “custom_type_def.svh”
module
(input custom_type_def ctd,
…
);
The problem is that sometimes when I am using the data type defined in the header file between multiple modules, I get something like the following runtime (after elaboration) error:
** Error: (vsim-7065) c:/Main_traffic_gen.svh(346): Illegal assignment to class work.main_tb_sv_unit::Test_pkt from class work.flex_main_tb_sv_unit::Test_pkt
I think the problem is that the type is being defined in multiple places, or the “unit” namespace of multiple modules, and that Questa does not know how to convert different instances of that type that is defined in more than one place. Is that correct? How is the best way to solve problems like this? There is no information that I can find about that error either online or using VERROR. And I cannot simply move the `include statement inside the module because the type is being used in the port map.
Thanks.