What is the work of disable iff (expression)?

SystemVerilog
,
1

What is the work of disable iff (expression)?
Can someone please tell this

2

In reply to big123:

It is an asynchronous reset. When the
disable iff expression is true, any active attempts of the property gets terminated (neither passes or fails).

3

In reply to dave_59:

Hi Dave,

Please look at the waves below:

1034×87 2.6 KB

for the following property:

property sig1_high_throughout_sig2 (sig1, sig2);
        $rose(sig2) |-> sig1 throughout ($rose(sig2) ##1 sig2[*1:$] ##1 $fell(sig2));
    endproperty

assert property (@(posedge test_clk iff rstb)sig1_high_throughout_sig2(sig1,!sig2));

Here, the assertion is enabled when rstb is 1. The rstb goes to 0 (disabling the assertion) then comes back up after a while. When it comes back up the assertion is resumed and consequently, fails. My understanding was that if the assertion is disabled, the ongoing check is terminated, and a new check will begin at the trigger condition.

Could you clarify if I have misunderstood it?
Could it be a tool issue?

Thanks
Ankit

4

In reply to Ankit Bhange:

You did not use the disable iff construct. I think you meant to write

assert property (@(posedge test_clk) disable iff (!rstb) sig1_high_throughout_sig2(sig1,!sig2));