What is the difference wire and logic?

SystemVerilog
,
1

Hi.

As far as I know, Wire and logic are no difference between two. but
I found a something difference between two in behavior. I’, already read Usage of Var | Verification Academy.

To pass the clock signal from clock_gen’s output aclk to control’s input clk I made a simple code as the below,


``` verilog
interface test_intf;
logic reset_n;
logic aclk;
logic bclk;
logic areset_n;

...

logic clk = aclk;
modport clock_gen (output aclk, bclk, areset_n);
modport control (input clk, reset_n);

and Test looks like

module test;
test_intf intf();

    CLKGEN u_CLKGEN (
                intf.clock_gen 
                    );
    CONTROL u_CONTROL(
            intf.control 
            );

initial begin
...

When I declare logic clk = aclk; then logic clk didn’t get signal from aclk.
But when I declare wire clk = aclk; instead, I can get the clock signal from aclk to clk.

Would you help me to understand what is the difference between wire and logic?

2

In reply to UVM_LOVE:

If you read the link above, you would know that

logic clk = aclk;

is implicitly

var logic clk = aclk;

and = aclk; is a once at time 0 static variable declaration initialization.


wire clk = aclk;

is implicitly

wire logic clk = aclk;

and = aclk; is a continuous assignment wire declaration.

Also see What's the deal with those wire’s and reg’s in Verilog - Verification Horizons