What is difference between below two code execution

SystemVerilog
, , , ,
1

Code 1:


class_p p1,p2;
p1 = new();
p2 = new();
p2 = p1;

Code 2:


class_p p1,p2;
p1 = new();
p2 = new p1;

What is difference between above two. I understand both are same. (like, p2 = new p1; would in turn do p2 = new; p2 = p1;)
But it is not. In code 1, variable changed in p1 will be reflected in p2. But in code 2 variable changed in p1 would not change value in p2.

2

Case 1 (p2 = p1):

In this case, two handles, p1 and p2 will point to the same memory, so when we change any variable using handle p1, as the location is common, p2 will get the same value.

Case 2 (p2 = new p1):

This is an example of shallow copy. Here, p2 will create an exact copy of p1, so two different memories are created. Initially, both the objects have the properties with same values, but as the location are different, the change in a variable of p1 would not affect in a variable of p2.

3

In reply to JDS:

case:1

p1,p2 both share same memory location so when ever you change p1 or p2 both will change.

case 2:
it is shallow copy : means only data will copy not the object.
if you do p2= new p1. it creats a copy of p1
example
p1.data =10;
p2= new p1;

now p2 will get the value (10) of p1 but each(p1,p2) point to their own objects .means they update independently

i am giving case 3:
deep copy : both objects and data are copied.